View LTC3403_283239.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC3403 1.5MHz, 600mA Synchronous Step-Down Regulator with Bypass Transistor
FEATURES
s s
DESCRIPTIO
s s s s s s s s s s
s s
Dynamically Adjustable Output from 0.3V to 3.5V Very Low Quiescent Current: Only 20A During Operation 600mA Output Current Internal P-Channel MOSFET Bypass Transistor High Efficiency: Up to 96% 1.5MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 2.5V to 5V Input Voltage Range Drives Optional External P-Channel MOSFET Shutdown Mode Draws < 1A Supply Current Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protected Available in 8-Lead 3mm x 3mm DFN Package
The LTC (R)3403 is a high efficiency monolithic synchronous buck regulator optimized for WCDMA power amplifier applications. The output voltage can be dynamically programmed from 0.3V to 3.5V. At VOUT > 3.6V an internal bypass P-channel MOSFET connects VOUT directly to VIN, eliminating power loss through the inductor. Selectable forced continuous mode enables fast VOUT response to the controlling input. Supply current is only 20A in Burst Mode(R) operation and drops to <1A in shutdown. The 2.5V to 5V input voltage range makes the LTC3403 ideally suited for single Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. Switching frequency is internally set at 1.5MHz, allowing the use of small surface mount inductors and capacitors. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. The LTC3403 is available in a low profile 8-lead 3mm x 3mm DFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation.
APPLICATIO S
s s
WCDMA Cell Phone Power Amplifiers Wireless Modems
TYPICAL APPLICATIO
VIN 2.7V TO 5V
2.2H* CIN 10F CER VIN MODE RUN REF SW GDR VOUT LTC3403 COUT** 4.7F CER
EFFICIENCY (%)
VOUT 3x VREF 600mA
OUTPUT PROGRAMMING DAC
GND 3 *MURATA LQH32CN2R2M11 **TAIYO YUDEN JMK212BJ475MG TAIYO YUDEN JMK212BJ106MN
WCDMA RF PA
3403 F01a
Figure 1a. WCDMA Transmitter Power Supply
U
95 90 85 80 75 70 65 60 55 50 0.1 FORCED CONTINUOUS MODE Burst Mode OPERATION VOUT = 1.8V 1 10 100 OUTPUT CURRENT (mA) 1000
3403 F01b
U
U
VIN = 3.6V VIN = 4.2V VIN = 3.6V VIN = 4.2V
Figure 1b. Efficiency vs Output Current
3403f
1
LTC3403
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GDR VIN GND SW 1 2 3 4 9 8 7 6 5 VOUT REF MODE RUN
Input Supply Voltage (< 300s) .................. - 0.3V to 6V Input Supply Voltage (DC) ....................... - 0.3V to 5.5V RUN, REF, MODE, VOUT, GDR Voltages ..... - 0.3V to VIN SW Voltage .................................. - 0.3V to (VIN + 0.3V) P-Channel Switch Source Current (DC) ............. 800mA N-Channel Switch Sink Current (DC) ................. 800mA Peak SW Sink and Source Current ........................ 1.3A Bypass P-Channel FET Source Current ...................... 1A Operating Temperature Range (Note 2) .. - 40C to 85C Junction Temperature (Note 3) ............................ 125C Storage Temperature Range ................ - 65C to 150C (DD Package) .................................... -65C to 125C
ORDER PART NUMBER LTC3403EDD
DD PACKAGE 8-LEAD (3mm x 3mm) PLASTIC DFN EXPOSED PAD IS GND (PIN 9) MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 43C/ W, JC = 3C/ W
DD PART MARKING LAAX
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 3.6V unless otherwise specified.
SYMBOL VOUT VOUT IPK VLOADREG VIN IS PARAMETER Regulated Output Voltage Output Voltage Line Regulation Peak Inductor Current Output Voltage Load Regulation Input Voltage Range Input DC Operating Current Burst Mode Operation Forced Continuous Mode Operation Shutdown Oscillator Frequency Bypass PFET Turn-Off Threshold Bypass PFET Turn-On Threshold RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET RDS(ON) of Bypass P-Channel FET SW Leakage Bypass PFET Leakage RUN Threshold RUN Input Current MODE Threshold MODE Input Current REF Input Current CONDITIONS VREF = 1.1V, MODE = VIN VREF = 0.1V, MODE = VIN VIN = 2.5V to 5V VIN = 3V, VREF = 0.9V
q q q
MIN 3.23 0.25 0.70
TYP 3.3 0.3 0.1 1 0.7
MAX 3.37 0.35 0.4 1.25 5
q
2.5 20 1.5 0.1 1.5 700 1.2 1.21 0.3 0.4 0.3 0.4 0.15 0.20 0.01 0.01 1 0.01 1.5 0.01 0.01
UNITS V V %/V A % V A mA A MHz kHz V V A A V A V A A
fOSC VREF RPFET RNFET RBYPASS ILSW ILBYP VRUN IRUN VMODE IMODE IREF
MODE = 0V, SW = Open MODE = VIN, SW = Open VRUN = 0V, VIN = 4.2V VREF 0.25V VREF 0.1V VREF = VREF = ISW = 160mA, Wafer Level ISW = 160mA, DD Package ISW = -160mA, Wafer Level ISW = -160mA, DD Package IOUT = 100mA, VIN = 3V, Wafer Level IOUT = 100mA, VIN = 3V, DD Package (Note 4) VRUN = 0V, VSW = 0V or 5V, VIN = 5V VOUT = 0V, VIN = 5V, VREF = 0V VRUN = 2.5V or 0V
q
1.2 550 1.167
35 2.5 1 1.8 850 1.26 0.4 0.4 0.18 1 1 1.5 1 2 1 1
q q q q q
0.3 0.3
2
U
3403f
W
U
U
WW
W
LTC3403
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3403E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3403: TJ = TA + (PD)(43C/W) Note 4: When VREF > 1.2V and VREF x3 > VIN, the P-channel FET will be on in parallel with the bypass PFET reducing the overall RDS(ON). Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs VIN
100 95 90 85 IL = 100mA
IL = 300mA IL = 600mA
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
80 75 70 65 60 55 50 2.5
IL = 10mA
3.0
3.5 VIN (V)
4.0
Efficiency vs Output Current
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.1 TA = 25C FORCED CONTINUOUS MODE Burst Mode OPERATION VOUT = 1.5V 1 10 100 OUTPUT CURRENT (mA) 1000
3403 G03
VIN = 3.6V VIN = 4.2V VIN = 4.2V
EFFICIENCY (%)
VIN = 3.6V
FREQUENCY (MHz)
UW
3403 G01
(From Figure 1a) Efficiency vs Output Current
100 90 80 VIN = 3.6V VIN = 4.2V VIN = 3.6V VIN = 4.2V
Efficiency vs VOUT
100 90 80 70 60 50 40 TA = 25C VIN = 3.6V 0 1 2 VOUT (V)
3403 GO1a
100mA BURST MODE 0PERATION
100mA FORCED CONTINUOUS MODE
70 60 50 40 30 20 10 4 0 0.1
600mA FORCED CONTINUOUS MODE
TA = 25C FORCED CONTINUOUS MODE Burst Mode OPERATION VOUT = 1.2V 1 10 100 OUTPUT CURRENT (mA) 1000
3403 G02
4.5
3
Efficiency vs Output Current
100 90 80 70 60 50 40 30 20 10 0 0.1 VIN = 3.6V VIN = 4.2V TA = 25C FORCED CONTINUOUS MODE Burst Mode OPERATION VOUT = 2.5V 1 10 100 OUTPUT CURRENT (mA) 1000
3403 G04
Oscillator Frequency vs Temperature
1.70 VIN = 3.6V 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125
VIN = 3.6V VIN = 4.2V
3403 G05
3403f
3
LTC3403 TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency vs Supply Voltage
1.8 TA = 25C 1600 1400
FREQUENCY (kHz)
OSCILLATOR FREQUENCY (MHz)
1.7 1.6 1.5 1.4 1.3 1.2
2
3 4 5 SUPPLY VOLTAGE (V)
Output Voltage vs Load Current
1.844 T = 25C A VIN = 3.6V 1.834
OUTPUT VOLTAGE (V)
1.824
RDS(ON) ()
1.814 1.804 1.794 1.784 1.774 0 100 200 300 400 500 600 700 800 900 1000 LOAD CURRENT (mA)
3403 G07
RDS(ON) vs Temperature
0.7 VIN = 2.7V 0.6 VIN = 4.2V 0.5
RDS(ON) () DYNAMIC SUPPLY CURRENT (A)
0.4 0.3 VIN = 3V 0.2 0.1 0 -50 -25 VIN = 4.2V MAIN SWITCH SYNCHRONOUS SWITCH BYPASS SWITCH 50 25 75 0 TEMPERATURE (C) 100 125 VIN = 3.6V
4
UW
(From Figure 1a)
Frequency vs VOUT
TA = 25C VIN = 3.6V
1200 1000 800 600 400
6
3403 G06
0
0.2
0.4
0.6 0.8 VOUT (V)
1.0
1.2
3403 F06a
RDS(ON) vs Input Voltage
0.7 0.6 0.5 0.4 0.3 0.2 BYPASS SWITCH 0.1 0 0 1 5 4 2 3 INPUT VOLTAGE (V) 6 7
3403 G08
TA = 25C MAIN SWITCH
SYNCHRONOUS SWITCH
Dynamic Supply Current vs Supply Voltage
4500 TA = 25C 4000 VOUT = 1.8V ILOAD = 0A 3500 3000 2500 2000 1500 1000 500 0 2 3 Burst Mode OPERATION 4 SUPPLY VOLTAGE (V)
3403 G09
3403 G10
VIN = 3.6V
FORCED CONTINUOUS MODE
5
6
3403f
LTC3403 TYPICAL PERFOR A CE CHARACTERISTICS (From Figure 1a)
Switch Leakage vs Temperature
300 VIN = 5.5V RUN = 0V 250
SWITCH LEAKAGE (nA)
100 SWITCH LEAKAGE (pA) 80 60 40 20 0 SYNCHRONOUS SWITCH 120
200 150 100 50 0 -50 -25 MAIN SWITCH SYNCHRONOUS SWITCH 50 25 75 0 TEMPERATURE (C) 100 125
Start-Up from Shutdown
RUN 2V/DIV VOUT 1V/DIV
IL 500mA/DIV
3403 G13 VIN = 3.6V 40s/DIV VREF = 0.6V RLOAD = 3 MODE = 3.6V, FORCED CONTINUOUS MODE
Forced Continuous Mode
VOUT 200mV/DIV IL 500mA/DIV
IL 200mA/DIV
VOUT 10mV/DIV
VIN = 3.6V VREF = 0.6V ILOAD = 0A MODE = 3.6V
UW
Switch Leakage vs Input Voltage
TA = 25C RUN = 0V
MAIN SWITCH
0
1
2 3 4 INPUT VOLTAGE (V)
5
6
3403 G12
3403 G11
Burst Mode Operation
VOUT 0.1V/DIV
IL 200mA/DIV
VIN = 3.6V VREF = 0.6V ILOAD = 60mA MODE = 0V
2s/DIV
3403 G14
Load Step Response
ILOAD 500mA/DIV VIN = 3.6V 20s/DIV VREF = 0.6V ILOAD = 50mA TO 600mA MODE = 0V, Burst Mode OPERATION
3403 G16
200ns/DIV
3403 G15
3403f
5
LTC3403 TYPICAL PERFOR A CE CHARACTERISTICS (From Figure 1a)
Load Step Response
VOUT 100mV/DIV IL 500mA/DIV ILOAD 500mA/DIV
VOUT 1V/DIV VREF 0.5V/DIV
3403 G17 VIN = 3.6V 20s/DIV VREF = 0.6V ILOAD = 0mA TO 600mA MODE = 0V, FORCED CONTINUOUS MODE
VOUT vs VREF
4.5 4.0 3.5 3.0 VIN = 4.2V IL = 100mA IL = 600mA
VOUT (V)
2.5 2.0 1.5 1.0 0.5 0 0 0.5 VREF (V)
3403 G19
6
UW
REF Transient
3403 G18 VIN = 4.2V 40s/DIV VREF = 0V TO 1.4V RLOAD = 5 MODE = 4.2V, FORCED CONTINUOUS MODE
Reference vs GDR
REF 1V/DIV
GDR 2V/DIV
VIN = 3.6V CGDR = 1000pF
1.0 1.5
5s/DIV
3403 F20
3403f
LTC3403
PI FU CTIO S
GDR (Pin 1): MOSFET Gate Driver. Drives a small external P-channel MOSFET. VIN (Pin 2): Main Supply Pin. Must be closely decoupled to GND, Pin 3, with a 10F or greater ceramic capacitor. GND (Pin 3): Ground Pin. SW (Pin 4): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. RUN (Pin 5): Run Control Input. Forcing this pin above 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing <1A supply current. Do not leave RUN floating. MODE (Pin 6): Mode Select Input. To select forced continuous mode, tie to VIN. Grounding this pin selects Burst Mode operation. Do not leave this pin floating. REF (Pin 7): External Reference Input. Controls the output voltage to 3x the applied voltage at REF. Also turns on the bypass MOSFET when VREF > 1.2V. VOUT (Pin 8): Output Voltage Feedback Pin. An internal resistive divider divides the output voltage down by 3 for comparison to the external reference voltage. The drain of the P-channel bypass MOSFET is connected to this pin. Exposed Pad (Pin 9): Connect to GND, Pin 3.
FU CTIO AL DIAGRA
MODE 6
SLOPE COMP OSC OSC
FREQ REF 7 VOUT 8 360k FB
/2
EA
180k P-CHANNEL VIN
-
BCMP 1.2V RUN 5
+
IRCMP
+
-
W
-
+
U
U
U
U
U
0.65V
2 VIN
- +
0.85V
- +
EN SLEEP
-
BURST Q Q SWITCHING LOGIC AND BLANKING CIRCUIT
ICOMP
+
5
S R
RS LATCH
ANTISHOOTTHRU
4 SW
9 3 GND 1 GDR
3403 BD
3403f
7
LTC3403
OPERATIO
Main Control Loop The LTC3403 uses a constant frequency, current mode step-down architecture. The main (P-channel MOSFET), synchronous (N-channel MOSFET) and bypass (P-channel MOSFET) switches are internal. During normal operation, the internal main switch is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage, FB, relative to the external reference, which in turn, causes the EA amplifier's output voltage to increase until the average inductor current matches the new load current. While the main switch is off, the synchronous switch is turned on until the beginning of the next clock cycle. In forced continuous mode the inductor current is constantly cycled. In this mode, the output voltage can respond quickly to the external reference voltage by sourcing or sinking current as needed. Burst Mode Operation The LTC3403 is capable of Burst Mode operation in which the internal power switches operate intermittently based on load demand. In Burst Mode operation, the peak current of the inductor is set to approximately 200mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. In between these burst events, the power switches and any unneeded circuitry are turned off, reducing the quiescent current to 20A. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage droops, the EA amplifier's output rises above the sleep threshold signal-
8
U
(Refer to Functional Diagram)
ing the BURST comparator to trip and turn the top switch on. This process repeats at a rate that is dependent on the load demand. Controlling the Output Voltage The output voltage can be dynamically programmed from 0.3V to 3.5V using the REF input. Because the gain to VOUT from REF is internally set to 3, the corresponding input range at REF is 0.1V to 1.167V. VOUT can be modulated during operation by driving REF with an external DAC. When REF exceeds 1.2V, an internal bypass P-channel MOSFET connects VIN to VOUT, dramatically reducing the drop across the inductor and the main switch. Dropout Operation If the reference voltage would cause VOUT to exceed VIN, the LTC3403 enters dropout operation. During dropout, the main switch remains on continuously and operates at 100% duty cycle. If the voltage at REF is less than 1.2V, the bypass P-channel MOSFET will stay off even in dropout operation. The output voltage is then determined by the input voltage minus the voltage drop across the main switch and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3403 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). Low Supply Operation The LTC3403 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is reduced at this low voltage. Figure 2 shows the reduction in the maximum output current as a function of input voltage for various output voltages.
3403f
LTC3403
OPERATIO
1200
MAXIMUM OUTPUT CURRENT (mA)
1000 800 600 400 200 0 VOUT = 1.8V VOUT = 2.5V VOUT = 1.5V
2.5
Figure 2. Maximum Output Current vs Input Voltage
APPLICATIO S I FOR ATIO
The basic LTC3403 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 1H to 4.7H. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. As Equation 1 shows, a greater difference between VIN and VOUT produces a larger ripple current. Where these voltages are subject to change, the highest VIN and lowest VOUT will determine the maximum ripple current. A reasonable starting point for setting ripple current is IL = 240mA (40% of the maximum load, 600mA).
V 1 IL = VOUT 1 - OUT VIN (f)(L)
At output voltages below 0.6V, the switching frequency decreases linearly to a minimum of approximately 700kHz. This places the maximum ripple current (in forced continuous mode) at the highest input voltage and the lowest output voltage. In practice, the resulting ouput ripple voltage is 10mV to 15mV using the components specified in Figure 1.
U
W
UU
U
3.0
(Refer to Functional Diagram)
Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3403 uses a patent-pending scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles.
3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
5.5
3403 F02
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 720mA rated inductor should be enough for most applications (600mA + 120mA). For better efficiency, choose a low DC-resistance inductor. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 200mA. Lower inductor values (higher IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price versus size requirements and any radiated field/EMI requirements than on what the LTC3403 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3403 applications.
3403f
(1)
9
LTC3403
APPLICATIO S I FOR ATIO
Table 1. Representative Surface Mount Inductors
Part Number Sumida CDRH2D11 Sumida CDRH2D18/LD Sumida CMD4D06 Murata LQH32C Taiyo Yuden LQLBC2518 Toko D412F Value (H) 1.5 2.2 3.3 2.2 3.3 4.7 2.2 3.3 4.7 1.0 2.2 4.7 1.0 1.5 2.2 2.2 3.3 4.7 DCR (MAX) 0.068 0.098 0.123 0.041 0.054 0.078 0.116 0.174 0.216 0.060 0.097 0.150 0.080 0.110 0.130 0.14 0.20 0.22 MAX DC Current (A) 0.90 0.78 0.60 0.85 0.75 0.63 0.95 0.77 0.75 1.00 0.79 0.65 0.78 0.66 0.60 1.14 0.90 0.80 Size WxLxH (mm3) 3.2 x 3.2 x 1.2
3.2 x 3.2 x 2.0
3.5 x 4.1 x 0.8
2.5 x 3.2 x 2.0
1.8 x 2.5 x 1.8
4.6 x 4.6 x 1.2
CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
CIN required IRMS IOMAX [VOUT (VIN - VOUT )]1/ 2 VIN
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question.
10
U
The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple VOUT is determined by:
1 VOUT IL ESR + 8f C OUT
W
UU
where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since IL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. The bulk capacitance values in Figure 1(a) (CIN = 10F, COUT = 4.7F) are tailored to mobile phone applications, in which the output voltage is expected to slew quickly according to the needs of the power amplifier. Holding the output capacitor to 4.7F facilitates rapid charging and discharging. When the output voltage descends quickly in forced continuous mode, the LTC3403 will actually pull current from the output until the command from VREF is satisfied. On alternate half cyles, this current actually exits the VIN terminal, potentially causing a rise in VIN and forcing current into the battery. To prevent deterioration of the battery, use sufficient bulk capacitance with low ESR; at least 10F is recommended.
3403f
LTC3403
APPLICATIO S I FOR ATIO
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3403's control loop does not depend on the output capacitor's ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Ceramic capacitors of Y5V material are not recommended because normal operating voltages cause their bulk capacitance to become much less than the nominal value. Programming the Output Voltage With a DAC The output voltage can be dynamically programmed to any voltage from 0.3V to 3.5V with an external DAC driving the REF pin. When the output is commanded low, the output voltage descends quickly in forced continuous mode pulling current from the output and transferring it to the input. If the input is not connected to a low impedance source capable of absorbing the energy, the input voltage could rise above the absolute maximum voltage of the part and get damaged. The faster VOUT is commanded low, the higher is the voltage spike at the input. For best results, ramp the REF pin from high to low as slow as the application will allow. Avoid abrupt changes in voltage of >0.2V/s. If ramp control is unavailable, an RC filter with a time constant of 10s can be inserted between the REF pin and the DAC as shown in Figure 3.
POWER LOSS (W)
U
10k DAC 1000pF LTC3403 REF GND
W
UU
Figure 3. Filtering the REF Pin
Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3403 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of little consequence as illustrated in Figure 4.
1 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V
0.1
0.01
0.001
0.0001
0.00001 0.1
1
10 100 LOAD CURRENT (mA)
1000
3406 F04
Figure 4. Power Lost vs Load Current
3403f
11
LTC3403
APPLICATIO S I FOR ATIO
1. The VIN quiescent current consists of two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN, thus, their effects will be more pronounced at higher supply voltages. (The gate charge of the bypass FET is, of course, negligible because it is infrequently cycled.) 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Hence, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In most applications the LTC3403 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3403 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance.
12
U
To prevent the LTC3403 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(JA) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3403 in dropout at an input voltage of 2.7V, a load current of 600mA (0.9V VREF < 1.2V) and an ambient temperature of 70C. With VREF < 1.2V, the entire 600mA flows through the main P-channel FET. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70C is approximately 0.52. Therefore, power dissipated by the part is: PD = (ILOAD2) * RDS(ON) = 187.2mW For the 8L DFN package, the JA is 43C/W. Thus, the junction temperature of the regulator is: TJ = 70C + (0.1872)(43) = 78C which is below the maximum junction temperature of 125C. Modifying this example, suppose that VREF is raised to 1.2V or higher. This turns on the bypass P-channel FET as well as the main P-channel FET. Assume that the inductor's DC resistance is 0.1, the RDS(ON) of the main P-channel switch is 0.52, and the RDS(ON) of the bypass P-channel switch is 0.21. The current through the P-channel switch and the inductor will be 152mA, causing power dissipation of (0.152A)2 * 0.62 = 14.3mW. The bypass FET will dissipate (0.448A)2 * 0.21 = 42.5mW. Thus, TJ = 70C + (0.0143 + 0.0425)(43) = 72.4C.
3403f
W
UU
LTC3403
APPLICATIO S I FOR ATIO
Reductions in power dissipation occur at higher supply voltages, where the junction temperature is lower due to reduced switch resistance (RDS(ON)). Further reductions may be achieved using an external bypass FET (Figure 5), which operates in parallel with the network described above. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD * ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 * CLOAD). Thus, a 10F capacitor charging to 3.3V would require a 250s rise time, limiting the charging current to about 130mA.
U
M1 LTC3403 VIN VIN SW GDR VOUT
LTC3403 F05
W
UU
VOUT
Figure 5. Driving an External Bypass FET
VOUT COUT 1 VIN CIN 2 GDR VIN VOUT REF MODE RUN 8 7 6 5 RREF DAC CREF
3 GND 4 SW
LTC3403
BOLD LINES INDICATE HIGH CURRENT PATHS
LTC3403 F06
Figure 6.Layout Diagram
3403f
13
LTC3403
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3403. These items are also illustrated graphically in Figures 6 and 7. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC drive to the internal power MOSFETs. 3. Keep the (-) plates of CIN and COUT as close as possible. Design Example As a design example, assume the LTC3403 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a
TO DAC
RREF
VIA TO REF
COUT CIN GDR VIN GND SW 1 2 LTC3403 3 4 6 5 MODE RUN CREF 8 7 VOUT REF
VIN 2.7V TO 5V 2 CIN 10F CER 10k 6 5 7 LTC3403 4 VIN SW MODE RUN REF GND 3 * MURATA LQH32CN2R2M11 ** TAIYO YUDEN JMK212BJ475MG TAIYO YUDEN JMK212BJ106MN
LTC3403 F08
L1
VIA TO GND
3403 F07
VIA TO VIN
Figure 7. Suggested Layout
14
U
maximum of 0.6A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using Equation (1),
L= V 1 VOUT 1 - OUT VIN (f)(IL )
W
UU
(2)
Substituting VOUT = 2.5V, VIN = 4.2V, IL = 240mA and f = 1.5MHz in Equation (2) gives:
L= 2.5V 2.5V 1- = 2.81H 1.5MHz (240mA) 4.2V
A 2.2H inductor works well for this application. For best efficiency choose a 720mA or greater inductor with less than 0.2 series resistance. CIN will require an RMS current rating of at least 0.3A LOAD(MAX)/2 at temperature and COUT will require an ESR of less than 0.25. In most cases, a ceramic capacitor will satisfy this requirement.
2.2H* VOUT COUT** 4.7F CER
GDR VOUT
1 8
DAC 1000pF
Figure 8
3403f
LTC3403
PACKAGE DESCRIPTIO
3.35 0.05 1.65 0.05 2.25 0.05 (2 SIDES) PACKAGE OUTLINE 0.28 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
DD Package 8-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 TYP 5 0.58 0.05 0.38 0.10 8 3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES)
(DD8) DFN 0902
0.200 REF
0.75 0.05
4 0.28 0.05 2.38 0.10 (2 SIDES)
1 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED
3403f
15
LTC3403
TYPICAL APPLICATIO
High Efficiency Step-Down Converter with External Bypass MOSFET
M1
VIN 2.7V TO 5V
RELATED PARTS
PART NUMBER LT1932 LT1937 LTC3200/LTC3200-5 LTC3250-1.5 DESCRIPTION Constant Current, 1.2MHz, High Efficiency White LED Boost Regulator Constant Current, 1.2MHz, High Efficiency White LED Boost Regulator Low Noise, 2MHz, Regulated Charge Pump White LED Driver 250mA,1.5MHz, High Efficiency Step Down Charge Pump COMMENTS Up to 8 White LEDs, VIN: 1V to 10V, VOUT(MAX): 34V, IQ: 1.2mA, ISD: <1A, ThinSOTTM Package Up to 4 White LEDs, VIN: 2.5V to 10V, VOUT(MAX): 34V, IQ: 1.9mA, ISD: <1A, ThinSOT, SC70 Packages Up to 6 White LEDs, VIN: 2.7V to 4.5V, IQ: 8mA, ISD: <1A, MSOP/ThinSOT Packages Up to 88% Efficiency, VIN: 3.1V to 5.5V, VOUT: 1.5V, IQ: 35A, ISD: <1A, ThinSOT Package Up to 88% Efficiency, VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V,1.5V; IQ: 8A, ISD: <1A, MS Package Up to 88% Efficiency, VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V, IQ: 60A, ISD: <1A, DFN-12 Package 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN): 0.8V, IQ: 20A, ISD: <1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 20A, ISD: <1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 2.5V to 5.5V, IQ: 25A, ISD: <1A, MSOP Package 95% Efficiency, VIN: 2.4V to 5.5V, VOUT: 1.5V to 5.25V, IQ: 25A, ISD: <1A, DFN-12 Package
LTC3251/LTC3251-1.5 500mA,Spread Spectrum, High Efficiency Step Down Charge Pump LTC3252 LTC3405/LTC3405A LTC3406/LTC3406B LTC3440 LTC3441 LT3465/LT3465A Dual 250mA/Channel,Spread Spectrum, High Efficiency Step Down Charge Pump 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 1A (IOUT), 1MHz, Synchronous Buck-Boost DC/DC Converter
Constant Current, 1.2MHz/2.7MHz, High Efficiency Up to 6 White LEDs, VIN: 2.7V to 16V, VOUT(MAX): 30V, IQ: 2mA, White LED Boost Regulator with Integrated Schottky Diode ISD: <1A, ThinSOT Package
ThinSOT is a trademark of Linear Technology Corporation.
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
2 CIN 10F CER 6 5 7 VIN MODE RUN REF GND 3 * MURATA LQH3C2R4M74 ** TAIYO YUDEN JMK212BJ475MG TAIYO YUDEN JMK212BJ106MN
3403 TA01
SW
4
4.7H*
LTC3403
1 GDR 8 VOUT
VOUT 3x REF COUT** 600mA 4.7F CER
CONTROL DAC
3403f LT/TP 0603 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

▲Up To Search▲

Price & Availability of LTC3403

	To Download LTC3403 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .